Automatic analog layout retargeting for new processes and device sizes

Autor:	C.-J.R. Shi, Roy Hartono, N. Jangkrajarng, Sambuddha Bhattacharya
Rok vydání:	2003
Předmět:	Standard cell Computer science Transistor Integrated circuit layout Circuit extraction law.invention Design layout record CMOS law Retargeting Hardware_INTEGRATEDCIRCUITS Electronic engineering Operational amplifier Cmos process Layout Versus Schematic IC layout editor
Zdroj:	ISCAS (4)
DOI:	10.1109/iscas.2003.1206224
Popis:	This paper presents an automatic analog layout resizing tool that can generate a new layout incorporating the target technology process and the target transistor sizes. The tool automatically preserves the analog layout integrity by extracting layout symmetry and matching, and then solving the constrained layout generation problem using a combined linear programming and graph-theoretic approach. The tool has been applied successfully to integrate specified transistor sizes and to migrate layouts for various analog designs from TSMC 0.25 /spl mu/m CMOS to TSMC 0.18 /spl mu/m CMOS process with comparable performances to re-design.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::d47f17c8aeb14ee1524bc7e3c3e152ae https://doi.org/10.1109/iscas.2003.1206224 Zobrazit plný text záznamu