Implementation of Low Delay Dual Chamber Pacemaker Using Verilog
| Autor: | Basant Kumar, Sonali Ray, Meenakshi Sharma, Ravi Prakash Tewari, Dinesh Bhatia, Nitin Sahai, Rohini Srivastava |
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| Rok vydání: | 2019 |
| Předmět: |
Dual Chamber Pacemaker
Computer science Beats per minute medicine.medical_treatment 010401 analytical chemistry 0206 medical engineering Low delay 02 engineering and technology 020601 biomedical engineering 01 natural sciences Cardiac pacemaker 0104 chemical sciences Heart rate cardiovascular system Heart beat medicine Verilog computer Simulation computer.programming_language |
| Zdroj: | 2019 6th International Conference on Signal Processing and Integrated Networks (SPIN). |
| DOI: | 10.1109/spin.2019.8711746 |
| Popis: | This paper presents a hardware implementation of Dual Chamber Cardiac Pacemaker for different ranges of heart beats with minimum delay. Proposed research work attempts to design and implement a low delay dual chamber demand pacemaker. Pacemakers are used for life-threatening disease such as arrhythmia. A minimum delay between sensing and pacing is very crucial for maintaining the adequate heart rate. Therefore the main motive of this work is to reduce the delay between sensing and pacing of the pacemaker. The demand pacemaker works in accordance with the heart rate of the patient who is suffering from arrhythmia and its range may be different for different patients. The range from 30 beats per minute (bpm) to 70 beats per minute (bpm) has been taken for the proposed work. The tool used for the proposed low delay dual chamber pacemaker is Xilinx 14.7. The result shows that the proposed work is better in terms of delay, computational complexity, and cost. |
| Databáze: | OpenAIRE |
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