| Popis: |
TSV is the key component in fabricating 3-D ICs which can bring lower power consumption, higher integration density and shorter interconnection length. Very few works on EM and TDDB of TSV have been done. Thus, TSV macros with BEOL and backside metal were designed and tested adventurously with EM and TDDB reliability perspective. For EM, the void, however, was found at Cu/SiN interface between TSV bottom and backside metal not at TSV itself due to unexpectedly strong reliability of TSV. And also the TDDB occurred at IMD not at TSV dielectric oxide layer. As a result, the minimum level of reliability of TSV has been obtained experimentally in silicon data at least although the reliability of TSV itself has not been assessed exactly. The guide lines for making reliability macros and testing conditions are suggested also by further investigation. |
