A Hardware Implementation of Arithmetic Operations for an FPGA-based Programmable Logic Controller
| Autor: | Miroslaw Chmiel, Józef Kulisz, Marcin Rosół, Adrian Krzyzyk |
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| Rok vydání: | 2015 |
| Předmět: |
Floating point
Comparator Computer science ComputerApplications_COMPUTERSINOTHERSYSTEMS Programmable logic array Instruction set Arithmetic logic unit Application-specific integrated circuit VHDL Arbitrary-precision arithmetic Saturation arithmetic Hardware_ARITHMETICANDLOGICSTRUCTURES Erasable programmable logic device Arithmetic Field-programmable gate array Simple programmable logic device Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION Register-transfer level Logic optimization computer.programming_language Digital electronics Function block diagram business.industry Logic family Programmable logic controller Macrocell array Complex programmable logic device Programmable logic device Programmable Array Logic Logic synthesis Control and Systems Engineering Logic gate Verilog business computer Computer hardware Hardware_LOGICDESIGN |
| Zdroj: | IFAC-PapersOnLine. 48:460-465 |
| ISSN: | 2405-8963 |
| Popis: | The paper presents the Arithmetic and Logic Unit (ALU) of a prototype Programmable Logic Controller (PLC), implemented in an FPGA device. The PLC implements on the machine language level a subset of the instruction set defined in the EN 61131-3 norm. The design was prepared as a set of synthesizable Verilog, and VHDL models. The ALU can execute 32 operations, which include the basic logic operations, comparators, and the four basic arithmetic operations. The operations can be performed for fixed-point, and floating-point numbers. All the operations are implemented fully in hardware, so the solution is fast. The HDL models used for synthesis can be easily ported to other FPGA architectures, or to an ASIC. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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