A 10Mbit, 15Gbytes/sec bandwidth 1R DRAM chip with planar MOS storage capacitor in an unmodified 150nm logic process for high-density on-chip memory applications

Autor:	Shih-Lien Lu, S. Borkar, B. Bloechel, K. Lai, Dinesh Somasekhar, G. Dermer, Vivek De
Rok vydání:	2005
Předmět:	Hardware_MEMORYSTRUCTURES business.industry Computer science Sense amplifier Bandwidth (signal processing) law.invention Capacitor Logic synthesis Software_SOFTWAREENGINEERING law Electronic engineering Optoelectronics Static random-access memory Cache business Access time Power density
Zdroj:	Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005..
DOI:	10.1109/esscir.2005.1541633
Popis:	A 10Mb planar 1T-IC DRAM chip is implemented in an unmodified 150nm micro-processor logic process. It achieves 15GBytes/sec bandwidth, 9.5nsec read access time with 197mW power at 1.5V, 110/spl deg/C. Worst-case refresh period is 100/spl mu/S at 110/spl deg/C with refresh power density of 0.18W/cm/sup 2/. Effective bit density of 42Mb/cm/sup 2/ is /spl sim/3/spl times/ better than the best 6T SRAM cache in the same technology.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::d39c8edd8f6b97a90f9adb738dcfd5ac https://doi.org/10.1109/esscir.2005.1541633 Zobrazit plný text záznamu