A digit-serial VLSI architecture for delayed LMS adaptive FIR filtering

Autor:	Chin-Liang Wang, Ching-Chia Chen, Che-Fu Chang
Rok vydání:	2002
Předmět:	Adaptive filter Least mean squares filter Recursive least squares filter Very-large-scale integration Finite impulse response Computer science Electronic engineering Filter (signal processing) Hardware_ARITHMETICANDLOGICSTRUCTURES Arithmetic Realization (systems) Digital filter
Zdroj:	ISCAS
DOI:	10.1109/iscas.1995.521571
Popis:	In this paper, we present a digit-serial VLSI architecture for realization of an adaptive FIR filter equipped with the delayed least mean square (LMS) algorithm. The architecture is attractive for use in applications where bit-serial arithmetic is too slow and bit-parallel arithmetic requires too much hardware or cannot reach the desired convergence performance.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::d34d14831f0a1c517879d13a0b1affdd https://doi.org/10.1109/iscas.1995.521571 Zobrazit plný text záznamu