Methodology to achieve planar technology-like ESD performance in FINFET process

Autor:	Jagar Singh, Konstantin Korablev, Jian-Hsing Lee, Mahadeva Iyer Natarajan, Manjunatha Prabhu, Shesh Mani Pandey
Rok vydání:	2015
Předmět:	Adder Materials science Planar Silicon chemistry Logic gate Hardware_INTEGRATEDCIRCUITS Process (computing) Electronic engineering chemistry.chemical_element Planar process Hardware_PERFORMANCEANDRELIABILITY Hardware_LOGICDESIGN
Zdroj:	IRPS
DOI:	10.1109/irps.2015.7112721
Popis:	Method for making Finfet ESD performance comparable to bulk planar ESD devices is demonstrated using a simple but effective process. Low FIN silicon volume compared to their counterparts in bulk planar process is compensated with the additional deep implants. The selected ESD devices in Finfet process show competitive ESD performance without any significant cost adder.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::d3333fdc11cb66f6ce15addbe0334d6c https://doi.org/10.1109/irps.2015.7112721 Zobrazit plný text záznamu