Pseudo-3D Physical Design Flow for Monolithic 3D ICs: Comparisons and Enhancements
| Autor: | Heechun Park, Bon Woong Ku, Sung Kyu Lim, Kyungwook Chang, Da Eun Shim |
|---|---|
| Rok vydání: | 2021 |
| Předmět: |
010302 applied physics
Computer science 02 engineering and technology Timing closure computer.software_genre 01 natural sciences Computer Graphics and Computer-Aided Design 020202 computer hardware & architecture Computer Science Applications Power (physics) Flow (mathematics) 0103 physical sciences Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering Computer Aided Design Electrical and Electronic Engineering Physical design computer |
| Zdroj: | ACM Transactions on Design Automation of Electronic Systems. 26:1-25 |
| ISSN: | 1557-7309 1084-4309 |
| Popis: | Studies have shown that monolithic 3D ( M3D ) ICs outperform the existing through-silicon-via ( TSV ) -based 3D ICs in terms of power, performance, and area ( PPA ) metrics, primarily due to the orders of magnitude denser vertical interconnections offered by the nano-scale monolithic inter-tier vias. In order to facilitate faster industry adoption of the M3D technologies, physical design tools and methodologies are essential. Recent academic efforts in developing an EDA algorithm for 3D ICs, mainly targeting placement using TSVs, are inadequate to provide commercial-quality GDS layouts. Lately, pseudo-3D approaches have been devised, which utilize commercial 2D IC EDA engines with tricks that help them operate as an efficient 3D IC CAD tool. In this article, we provide thorough discussions and fair comparisons (both qualitative and quantitative) of the state-of-the-art pseudo-3D design flows, with analysis of limitations in each design flow and solutions to improve their PPA metrics. Moreover, we suggest a hybrid pseudo-3D design flow that achieves both benefits. Our enhancements and the inter-mixed design flow, provide up to an additional 26% wirelength, 10% power consumption, and 23% of power-delay-product improvements. |
| Databáze: | OpenAIRE |
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