Wideband multi-bit third-order sigma-delta ADC for wireless transceivers

Autor:	Ho-Yeon Lee Ho-Yeon Lee, Dong-Yong Kim, Seok-Woo Choi, Sun-Hong Kim
Rok vydání:	2003
Předmět:	Third order Computer science Clock rate Electronic engineering Baseband Oversampling Topology (electrical circuits) computer.file_format Hardware_ARITHMETICANDLOGICSTRUCTURES Wideband Delta-sigma modulation computer Data conversion
Zdroj:	2003 5th International Conference on ASIC Proceedings (IEEE Cat No 03TH8690) ICASIC-03.
DOI:	10.1109/icasic.2003.1277642
Popis:	This paper presents a multi-bit sigma-delta data converter with third-order 3-bit topology. This converter can achieve high resolution with a lower order modulator and lower oversampling ratio than single-bit converter. The dynamic element matching (DEM) algorithm is designed in such a way as to minimize delay within the feedback loop of the sigma-delta ADC. The behavioral model is used to simulate the designed sigma-delta data converter. The designed ADC achieves 14-bit resolution, a peak SNR of 87dB within a 1 MHz signal baseband at a clock rate of 50MHz.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::d1e3f9bd4d8083ecca21140bb442fd17 https://doi.org/10.1109/icasic.2003.1277642 Zobrazit plný text záznamu