A Synthesis Methodology for Ternary Logic Circuits in Emerging Device Technologies
| Autor: | Bodapati Srinivasu, K. Sridharan |
|---|---|
| Rok vydání: | 2017 |
| Předmět: |
Digital electronics
Adder Unary operation business.industry 020208 electrical & electronic engineering 02 engineering and technology 021001 nanoscience & nanotechnology Hardware and Architecture Barrel shifter Logic gate 0202 electrical engineering electronic engineering information engineering Benchmark (computing) Electronic engineering Electrical and Electronic Engineering 0210 nano-technology Ternary operation business Hardware_LOGICDESIGN Mathematics Electronic circuit |
| Zdroj: | IEEE Transactions on Circuits and Systems I: Regular Papers. 64:2146-2159 |
| ISSN: | 1558-0806 1549-8328 |
| Popis: | Automatic synthesis of digital circuits has played a key role in obtaining high-performance designs. While considerable work has been done in the past, emerging device technologies call for a need to re-examine the synthesis approaches, so that better circuits that harness the true power of these technologies can be developed. This paper presents a methodology for synthesis applicable to devices that support ternary logic. We present an algorithm for synthesis that combines a geometrical representation with unary operators of multivalued logic . The geometric representation facilitates scanning appropriately to obtain simple sum-of-products expressions in terms of unary operators. An implementation based on Python is described. The power of the approach lies in its applicability to a wide variety of circuits. The proposed approach leads to the savings of 26% and 22% in transistor-count, respectively, for a ternary full-adder and a ternary content-addressable memory (TCAM) over the best existing designs. Furthermore, the proposed approach requires, on an average, less than 10% of the number of the transistors in comparison with a recent decoder-based design for various ternary benchmark circuits. Extensive HSPICE simulation results show roughly 92% reduction in power-delay product (PDP) for a $12\times 12$ TCAM and 60% reduction in PDP for a 24-ternary digit barrel shifter over recent designs. |
| Databáze: | OpenAIRE |
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