FinFET resistance mitigation through design and process optimization

Autor:	Zhibin Ren, Josephine B. Chang, Munir D. Naeem, Judson R. Holt, Omer H. Dokumaci, Qingyun Yang, Kevin K. Chan, Arvind Kumar, John King, Xinlin Wang, John Yates, Cindy Wang, Jin Cho, Thomas S. Kanarsky, C. Ouyang, Andreas Bryant, Yongsik Moon, Ying Zhang, Andreas Gehring, Dae-Gyu Park, Marwan H. Khater, Michael A. Guillorn, Chung-Hsun Lin, Wilfried Haensch, Amlan Majumdar, Xi Li
Rok vydání:	2009
Předmět:	Materials science Parasitic capacitance business.industry Logic gate Contact resistance Parasitic element MOSFET Electronic engineering Electrical engineering Node (circuits) Process optimization business Capacitance
Zdroj:	2009 International Symposium on VLSI Technology, Systems, and Applications.
DOI:	10.1109/vtsa.2009.5159323
Popis:	The intrinsic FinFET device structure can provide an estimated 10–20% reduction in delay relative to planar FETs at the 22nm technology node due to superior electrostatics. However, FinFETs are more prone to parasitic resistance and capacitance due to the thin body channel and 3-dimensional device architecture. Here we present strategies for minimizing FinFET parasitic resistance, and discuss overall device design optimization. Using FinFETs built at 45nm node dimensions, we have demonstrated FinFETs with an NFET/PFET external resistance of 230/350 Ω-um.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::d19c2b2f90f4ab0e9e73331d3d4c0c1b https://doi.org/10.1109/vtsa.2009.5159323 Zobrazit plný text záznamu