RSA processor design with vedic multiplier for nodes in wireless sensor networks
| Autor: | K. R. Venugopal, Shaila K, G. Leelavathi |
|---|---|
| Rok vydání: | 2017 |
| Předmět: |
Computer science
business.industry Processor design 020208 electrical & electronic engineering Prime number 02 engineering and technology Multiplier (Fourier analysis) Public-key cryptography 0202 electrical engineering electronic engineering information engineering 020201 artificial intelligence & image processing Multiplier (economics) Multiplication Hardware_ARITHMETICANDLOGICSTRUCTURES business Field-programmable gate array Wireless sensor network Computer hardware |
| Zdroj: | 2017 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET). |
| DOI: | 10.1109/wispnet.2017.8299964 |
| Popis: | Due to the resource constraints of Wireless Sensor Nodes the fast multipliers are essential for data processing. In this paper, we propose the RSA processor using Vedic multiplication technique that achieves considerable speed and with reduced area utilization. To multiply two prime numbers we have implemented Nikhilam and Urdva Triyagbagam multipliers. The results of our Hardware implementation on Xilinx Spartan III FPGA can be used for the construction of security architecture in WSN. The delay and area tradeoff leads to the selection of multiplier for RSA processor. The comparative analysis of the two different methodologies is analyzed in terms of speed and area. Urdva Triyagbagam gives good improvement in delay and device utilization compared to Nikhilam Multiplier. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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