Automated test bench generation for high-level synthesis flow ABELITE

Autor:	Raimund Ubar, Taavi Viilukas, Jaan Raik, Maksim Jenihhin, Samary Baranov
Rok vydání:	2011
Předmět:	Test bench Functional verification Computer science business.industry media_common.quotation_subject Code coverage Automatic test pattern generation Computer engineering Debugging Digital pattern generator High-level synthesis Algorithm design business Computer hardware media_common
Zdroj:	EWDTS
DOI:	10.1109/ewdts.2011.6116601
Popis:	The paper presents an approach for integration of automatic test bench generation based on a hierarchical test pattern generator Decider into the high-level synthesis flow Abelite. While the high-level synthesis flow provides fast results of complex systems design, functional verification of the design including initial specification has remained until now a sophisticated manual process. The automatically generated test benches provide high code coverage for simulation and are readable for debug. The experiments demonstrate viability and efficiency of the proposed approach.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::d147e123e77e30dfc53fb99c3cd7c6cb https://doi.org/10.1109/ewdts.2011.6116601 Zobrazit plný text záznamu