| Autor: |
Ghavam G. Shahidi, Terry I. Chappell, M.R. Polcari, Peter W. Cook, Carl J. Anderson, B.A. Chappell, Bijan Davari, James H. Comfort, M. G. Rosenfield, Stanley E. Schuster, R.L. Franch, Tak H. Ning, Robert H. Dennard |
| Rok vydání: |
2002 |
| Předmět: |
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| Zdroj: |
Proceedings of IEEE International Electron Devices Meeting. |
| Popis: |
In this paper a CMOS technology that is optimum for low voltage (in the I-volt range) applications is presented. Thin but undepleted SOI is used as the substrate, which gives low junction capacitance and no body effect. Furthermore floating body effects causes a reduction of subthreshold slope at high drain bias. This lowers the high-V/sub DS/ threshold to be used, which increases the current drive without significant increase in the off-current. This technology was applied to a high performance 512 Kb SRAM. Access time of 3.5 ns at 1 V was obtained. > |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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