Impact of e-SiGe S/D processes on FinFET PFET TDDB reliability
| Autor: | Andreas Kerber, Mahadeva Iyer Natarajan, B. Parameshwaran, C. LaRow, T. Nigam, Rakesh Ranjan, H. Yu, Suresh Uppal |
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| Rok vydání: | 2017 |
| Předmět: |
010302 applied physics
Materials science Dielectric strength business.industry Gate dielectric Electrical engineering Time-dependent gate oxide breakdown 02 engineering and technology 021001 nanoscience & nanotechnology 01 natural sciences Logic gate 0103 physical sciences Trench Surface roughness Optoelectronics Process optimization 0210 nano-technology business Layer (electronics) |
| Zdroj: | 2017 IEEE Electron Devices Technology and Manufacturing Conference (EDTM). |
| DOI: | 10.1109/edtm.2017.7947492 |
| Popis: | The impact of source/drain e-SiGe process engineering on time dependent dielectric breakdown (TDDB) on core PFETs fabricated with bulk FinFET technology is evaluated. It is observed that thicker e-SiGe buffer layer improves the PFETs TDDB. Electrical and physical analysis revealed that with thinner buffer layer, Ge atoms migrate to gate dielectric and accelerate the breakdown mechanisms due to poor surface roughness and stoichiometry. In addition, the process optimization of pre-baking of e-SiGe trench can also improve the TDDB even for relatively thinner buffer layer. |
| Databáze: | OpenAIRE |
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