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Within DARPA's Advanced Speech Encoding (ASE) program [1], BBN developed a series of noise-robust vocoder (NRV) algorithms and had them tested at an independent evaluation facility. With transmitted data rates as low as 300 bps, these NRV algorithms yield superior speech intelligibility, as compared to the 2400 bps enhanced Mixed Excitation Linear Prediction (MELPe) vocoder, in extremely harsh noise environments. NRV algorithms achieve their superior performance using an advanced wideband spectrum analysis procedure, known as spectral hypothesis testing, that compares each noisy multi-frame block of microphone output signal against hierarchically-structured speech and noise spectral trajectory codebooks. While the benefits for NRV speech coding are dramatic, spectral hypothesis testing places significant demand on encoder memory bandwidth. This created a challenge for real-time NRV operation. In 2009, BBN addressed this challenge by creating a hardware prototype with a simple coprocessor design. To assist the DSP, an FPGA supports the high-bandwidth memory access and modest number of operations needed for 300 bps real-time operation. |
