A 3.0 Gb/s Throughput Hardware-Efficient Decoder for Cyclically-Coupled QC-LDPC Codes
| Autor: | Jianfeng Fan, Wai M. Tam, Chiu-Wing Sham, Qing Lu, Francis C. M. Lau |
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| Rok vydání: | 2016 |
| Předmět: |
Block code
Computer science business.industry Clock rate 020206 networking & telecommunications 02 engineering and technology Serial concatenated convolutional codes Parallel computing 020202 computer hardware & architecture 0202 electrical engineering electronic engineering information engineering Bit error rate Turbo code Electrical and Electronic Engineering Low-density parity-check code business Throughput (business) Computer hardware Decoding methods |
| Zdroj: | IEEE Transactions on Circuits and Systems I: Regular Papers. 63:134-145 |
| ISSN: | 1558-0806 1549-8328 |
| DOI: | 10.1109/tcsi.2015.2510619 |
| Popis: | In this paper, we propose a new class of quasi-cyclic low-density parity-check (QC-LDPC) codes, namely cyclically-coupled QC-LDPC (CC-QC-LDPC) codes, and their RAM-based decoder architecture. CC-QC-LDPC codes have a simple structure and are constructed by cyclically-coupling a number of QC-LDPC subcodes. They can achieve throughput and error performance as excellent as LDPC convolutional codes, but with much lower hardware requirements. They are therefore promising candidates for future generations of communication systems such as long-haul optical communication systems. In particular, a rate-5/6 CC-QC-LDPC decoder has been implemented onto a field-programmable gate array (FPGA) and it achieves a throughput of 3.0 Gb/s at 100 MHz clock rate with 10-iteration decoding. No error floor is observed up to an $E_{b}/N_{0}$ of 3.50 dB, where all $1.14\times 10^{16}$ transmitted bits have been decoded correctly. |
| Databáze: | OpenAIRE |
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