High-Performance and Low-Power CMOS Device Technologies Featuring Metal/High-k Gate Stacks with Uniaxial Strained Silicon Channels on (100) and (110) Substrates

Autor:	S. Kanda, Yoshiya Hagimoto, M. Saito, Yuki Miyanami, Naoki Nagashima, Toyotaka Kataoka, R. Yamamoto, T. Ohchi, Y. Tateshita, K. Nagano, J. Wang, Hayato Iwamoto, Yoshiaki Kikuchi, Masanori Tsukamoto, K. Kugimiya, Kaori Tai, Tadayuki Kimura, Takashi Ando, Hitoshi Wakabayashi, Shigeru Fujita, T. Hirano, Y. Yamamoto, C. Yamane, Y. Tagawa, S. Yamaguchi, Yoshihiko Nagahama, T. Ikuta, R. Matsumoto, Shingo Kadomura
Rok vydání:	2006
Předmět:	Materials science business.industry Copper interconnect chemistry.chemical_element Strained silicon Epitaxy chemistry CMOS Low-power electronics Electronic engineering Optoelectronics business Tin Leakage (electronics) High-κ dielectric
Zdroj:	2006 International Electron Devices Meeting.
DOI:	10.1109/iedm.2006.346959
Popis:	CMOS technologies using metal/high-k damascene gate stacks with uniaxial strained silicon channels were developed. Gate electrodes of HfSix and TiN were applied to nFETs and pFETs, respectively. TiN/HfO2 damascene gate stacks and epitaxial SiGe source/drains were successfully integrated for the first time. As a result, drive currents of 1050 and 710 muA/mum at Vdd=l V, Ioff=100 nA/um and Tinv=1.6 nm were obtained for the nFETs and pFETs. The further integration of pFETs on (110) substrates contributed to a higher drive current of 830 muA/mum. These performances were realized under low gate leakage currents of 0.03 A/cm2 and below
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::cf7c214748a6db19d357723f8f79ba02 https://doi.org/10.1109/iedm.2006.346959 Zobrazit plný text záznamu