| Popis: |
Logic emulation systems based on FPGAs are becoming a widely accepted solution for the verification of large, complex designs. However, the acceptance of this technology is still lagging for the verification of ASIC designs with 50,000 gates or less of custom logic. This paper presents Project Spinnaker, a project aimed at the development of a rapid prototyping solution for this market segment. The project emphasizes what are believed to be the three key aspects for broadening the acceptance of the emulation verification methodology among ASIC designers: speed, cost, and automation. > |
