Efficient Path Delay Test Generation for Custom Designs
| Autor: | Bill Underwood Underwood, Haluk Konuk, Wai-on Law, Sungho Kang Kang |
|---|---|
| Rok vydání: | 2001 |
| Předmět: |
Very-large-scale integration
Engineering General Computer Science business.industry Circuit design Integrated circuit Test method Electronic Optical and Magnetic Materials law.invention Test (assessment) Computer engineering law Logic gate Benchmark (computing) Electronic engineering Electrical and Electronic Engineering business Hardware_LOGICDESIGN Electronic circuit |
| Zdroj: | ETRI Journal. 23:138-150 |
| ISSN: | 1225-6463 |
| DOI: | 10.4218/etrij.01.0101.0306 |
| Popis: | Due to the rapidly growing complexity of VLSI circuits, test methodologies based on delay testing become popular. However, most approaches cannot handle custom logic blocks which are described by logic functions rather than by circuit primitive elements. To overcome this problem, a new path delay test generation algorithm is developed for custom designs. The results using benchmark circuits and real designs prove the efficiency of the new algorithm. The new test generation algorithm can be applied to designs employing intellectual property (IP) circuits whose implementation details are either unknown or unavailable. |
| Databáze: | OpenAIRE |
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