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The performance of deep submicron devices depends heavily on the electrical properties of the gate dielectric. Electrical properties such as dielectric constant, leakage current density, interface trap and oxide trapped charge, dielectric integrity, and reliability are all critical concerns for the development of advanced gate dielectrics. This paper discusses several metrology methods based on capacitance-voltage (CV), charge-voltage (QV) and current-voltage (IV) and reviews the problems, issues and concerns associated with CV and IV metrology as IC technology has gone from 1 μm down to 0.18 μm and beyond. Issues such as proper measurement setup, equivalent circuit effects, silicon accumulation capacitance, and quantum confinement of the silicon density of states must be accounted for. In addition to these considerations, the influence of interfacial layers between the gate and the dielectric needs to be addressed. These interfacial layers can consist of organics, inorganics, and water. The paper include... |
