Low Power Wide Fan-in Domino OR Gate Using CN-MOSFETs
| Autor: | Bal Chand Nagar, Deepika Bansal, Ashok Kumar, Brahamdeo Prasad Singh |
|---|---|
| Rok vydání: | 2020 |
| Předmět: |
0209 industrial biotechnology
Control and Optimization OR gate Computer Networks and Communications business.industry Computer science Electrical engineering Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology Fan-in Domino Computer Science Applications Power (physics) 020901 industrial engineering & automation Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering 020201 artificial intelligence & image processing Electrical and Electronic Engineering business Hardware_LOGICDESIGN |
| Zdroj: | International Journal of Sensors, Wireless Communications and Control. 10:55-62 |
| ISSN: | 2210-3279 |
| DOI: | 10.2174/2210327909666190207163639 |
| Popis: | Background & Objective: In this paper, a modified pseudo domino configuration has been proposed to improve the leakage power consumption and Power Delay Product (PDP) of dynamic logic using Carbon Nanotube MOSFETs (CN-MOSFETs). The simulations for proposed and published domino circuits are verified by using Synopsys HSPICE simulator with 32nm CN-MOSFET technology which is provided by Stanford. Methods: The simulation results of the proposed technique are validated for improvement of wide fan-in domino OR gate as a benchmark circuit at 500 MHz clock frequency. Results: The proposed configuration is suitable for cascading of the high performance wide fan-in circuits without any charge sharing. Conclusion: The performance analysis of 8-input OR gate demonstrate that the proposed circuit provides lower static and dynamic power consumption up to 62 and 40% respectively, and PDP improvement is 60% as compared to standard domino circuit. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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