A Time-/Frequency-Domain Side-Channel Attack Resistant AES-128 and RSA-4K Crypto-Processor in 14-nm CMOS
Autor: | Xiaosen Liu, Vivek De, Sudhir K. Satpathy, Sanu Mathew, Harish K. Krishnamurthy, Krishnan Ravichandran, Himanshu Kaul, Vikram B. Suresh, Mark A. Anders, Raghavan Kumar |
---|---|
Rok vydání: | 2021 |
Předmět: |
Computer science
business.industry 020208 electrical & electronic engineering Advanced Encryption Standard Byte Cryptography 02 engineering and technology Power (physics) CMOS Frequency domain 0202 electrical engineering electronic engineering information engineering Side channel attack Time domain Electrical and Electronic Engineering Arithmetic business |
Zdroj: | IEEE Journal of Solid-State Circuits. 56:1141-1151 |
ISSN: | 1558-173X 0018-9200 |
DOI: | 10.1109/jssc.2021.3052146 |
Popis: | A side-channel attack (SCA) hardened AES-128 and RSA crypto-processor in 14-nm CMOS with measured resistance to correlation power/electromagnetic analysis (CPA/CEMA) in both time and frequency domains is demonstrated. While previously reported linear low-dropout regulators (LDOs) offer improvements in minimum-time-to-disclose (MTD) of extracted key bytes in the time domain, their transformations are less effective against frequency-domain attacks. This article describes a non-linear digital LDO (NL-DLDO) with control loop randomizations that bolster SCA resistance in the frequency domain. The NL-DLDO cascaded with an AES engine augmented with arithmetic countermeasures enables $>250\text{K}\times $ improvement in MTD, with no CPA/CEMA/DNN attacks detected after 1-B encryptions, with 8% power and 10% area overheads incurred by arithmetic techniques. The RSA-4K crypto-processor implements exponent magnitude and timing randomizations along with dynamic memory addressing to mitigate time- and frequency-domain attacks. The countermeasures enable $711\times $ suppression in means separation in current/EM magnitudes from 3.1 mV to $4.35~\mu \text{V}$ , reducing attacker’s accuracy to an ineffective random guess classification, while limiting area and performance overheads to < 0.05% and 3.25%, respectively. |
Databáze: | OpenAIRE |
Externí odkaz: |