A design of 4.19MHz real time clock generator with triple mode for fast settling, current reduction and low noise in 0.18um CMOS

Autor: Ju-Hyun Park, Sung Han Do, Kang-Yoon Lee, SungJin Kim, Ho-Cheol Ryu
Rok vydání: 2016
Předmět:
Zdroj: 2016 International Conference on Electronics, Information, and Communications (ICEIC).
DOI: 10.1109/elinfocom.2016.7562933
Popis: This paper presents triple mode to optimize settling, current consumption and noise of a crystal oscillator (XTAL). The proposed XTAL driver has three mode. Fast settling mode is used to reduce settling time. To reduce the start-up time of a XTAL driver, internal noise booster (INB) and negative resistance booster (NRB) are proposed. The simulated start-up time of a 4.19403MHz XTAL Driver in 0.18um CMOS is reduced by 80% from 4ms to 800us. Retention mode is only operated in stand-by to reduce total power consumption. A Peak and Low detection (PLD) is proposed. The stand-by of the XTAL driver does not effect to load. Therefore, the PLD blocks input supply voltage until HVT signal goes to down. It reduces power consumption up to 60%. EMI reduction mode is proposed to reduce output spur noise. To reduce output spur noise, pseudo-orandom-number generator (PRNG) is used makes 4bits random signal to spread frequency up to −10dB. All mode is controlled by Digital Control block. An inverter amplifier driver is optimized to reduce power consumption to 30uA and gets ± 100 ppm operation in changing temperature from −40°C to 60°C.
Databáze: OpenAIRE