An ASIC Implementation of the AES SBoxes

Autor:	Johannes Wolkerstorfer, Mario Lamberger, Elisabeth Oswald
Rok vydání:	2007
Předmět:	Combinational logic Standard cell business.industry Computer science Pipeline (computing) Advanced Encryption Standard Clock rate Encryption Finite field Application-specific integrated circuit Transistor count Embedded system Finite field arithmetic Hardware_ARITHMETICANDLOGICSTRUCTURES business
Zdroj:	Topics in Cryptology — CT-RSA 2002 ISBN: 9783540432241 CT-RSA
Popis:	This article presents a hardware implementation of the S-Boxes from the Advanced Encryption Standard (AES). The SBoxes substitute an 8-bit input for an 8-bit output and are based on arithmetic operations in the finite field GF(28). We show that a calculation of this function and its inverse can be done efficiently with combinational logic. This approach has advantages over a straight-forward implementation using read-only memories for table lookups. Most of the functionality is used for both encryption and decryption. The resulting circuit offers low transistor count, has low die-size, is convenient for pipelining, and can be realized easily within a semi-custom design methodology like a standard-cell design. Our standard cell implementation on a 0.6 ?m CMOS process requires an area of only 0.108 mm2 and has delay below 15 ns which equals a maximum clock frequency of 70 MHz. These results were achieved without applying any speed optimization techniques like pipelining.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::cdb3ec5868599ba0ffbb294f8fbb90a0 https://doi.org/10.1007/3-540-45760-7_6 Zobrazit plný text záznamu