N-FinFET based resistive keeper circuit for low power dynamic logic
| Autor: | Mahbubul Haque, Satyendra N. Biswas, Kazi Fatima Sharif, Riazul Islam, Marzia Akhter Keka |
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| Rok vydání: | 2017 |
| Předmět: |
Very-large-scale integration
Resistive touchscreen Pass transistor logic Computer science business.industry Electrical engineering Logic family 020207 software engineering Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology 020202 computer hardware & architecture Noise margin Logic gate Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering business Dynamic logic (digital electronics) Hardware_LOGICDESIGN Logic optimization |
| Zdroj: | 2017 International Conference on Innovative Mechanisms for Industry Applications (ICIMIA). |
| DOI: | 10.1109/icimia.2017.7975600 |
| Popis: | Dynamic logic is most area effective technique for designing VLSI circuit. However, due to lower noise margin of dynamic logic performance is not auspicious. This research proposes a N-FinFET based resistive keeper circuit using 45nm PTM FinFET model which reduces the contention between pull down network and keeper device using the special feature of four terminal FinFET (capacitance merging among both gates of four terminal FinFET). Proposed resistive gate voltage can control the strength of keeper device which reduces the leakage power and time delay. Extensive simulation results using LTSpice tools demonstrate the validity and superiority of the introduced circuit. |
| Databáze: | OpenAIRE |
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