A Low-Power and Highly Linear 14-bit Parallel Sampling TDC With Power Gating and DEM in 65-nm CMOS
| Autor: | Supeng Liu, Yuanjin Zheng |
|---|---|
| Rok vydání: | 2016 |
| Předmět: |
Power gating
Differential nonlinearity Pulse (signal processing) Computer science 020208 electrical & electronic engineering Buffer amplifier Delay line oscillator 020206 networking & telecommunications 02 engineering and technology Ring oscillator Chip Particle detector Integral nonlinearity CMOS Sampling (signal processing) Hardware and Architecture Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering Electrical and Electronic Engineering Software Leakage (electronics) |
| Zdroj: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 24:1083-1091 |
| ISSN: | 1557-9999 1063-8210 |
| DOI: | 10.1109/tvlsi.2015.2447001 |
| Popis: | This paper describes time-to-digital conver- ter (TDC) architecture capable of achieving subgate-delay resolution and large detection range at the same time with low power consumption. The proposed TDC is based on a parallel sampling ring oscillator with power gating and dynamic element matching (DEM). Through digital background calibration, the time resolution is determined by the delay difference between successive sampling clocks instead of buffer delay. The ring oscillator is enabled only during the incoming time pulsewidth, leading to low power consumption. A new buffer circuit implementation which enables the ring oscillator to settle to a known position after the ring oscillator stops is proposed. Furthermore, the stop position is latched by cross-coupled inverters to achieve immunity to leakage issues. For each incoming time pulse, the ring oscillator starts oscillation from the buffer before which the previous conversion stops, and thus, it also achieves barrel-shift algorithm for DEM and mitigates buffer mismatch impact. The design is fabricated in 65-nm CMOS technology and occupies a 0.4 mm $\times 0.3$ mm chip area. Measurements of the prototype IC demonstrate a detection range of 98 ns with 6 ps/LSB. It consumes $280~\mu \text{W}$ from a 1.2 V power supply when operating at a 1-MS/s sampling rate. The measured integral nonlinearity and differential nonlinearity are 0.5 and 0.1 LSB, respectively. Measurements of the prototype IC also demonstrate a single-shot precision of less than 11 ps. |
| Databáze: | OpenAIRE |
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