Scan methodology and ATPG DFT techniques at lower technology node
| Autor: | Haresh A. Suthar, Janki Chauhan, Chintan Panchal |
|---|---|
| Rok vydání: | 2017 |
| Předmět: |
Very-large-scale integration
0209 industrial biotechnology business.industry Computer science Design for testing 0211 other engineering and technologies Scan chain Test compression Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology Automatic test pattern generation 020901 industrial engineering & automation Embedded system Node (circuits) Electronic design automation business Computer hardware Testability 021106 design practice & management |
| Zdroj: | 2017 International Conference on Computing Methodologies and Communication (ICCMC). |
| Popis: | As VLSI Technology is continuously shrinking to lower technology nodes, we need efficient techniques for testing on lower nodes because as Design Complexity grows, there are numbers of challenges including higher test cost, higher power consumption, test time, area, pin count and new defects at small geometries(variation in transistor's channel length, W/L ratio, threshold voltage). Reliability and testability both are the important parameters in today's VLSI design. We use design for testability for this purpose. Scan is the first step for inserting DFT(design for testability) architecture in any chip. Thus scan insertion improves the controllability and observability of the sequentially flops. After that pattern generation step is there which is generated by ATPG (Automatic test pattern generation) Tool and finally pattern simulation will give results in terms of pass/fail patterns. The purpose of this paper is to implement scan insertion flow architecture on lower technology nodes and detect the targeted faults through the pattern generation by ATPG which will improve the yield on SOC by fault detection using some EDA tools. It also includes the optimization of the most important test parameters related to testability. |
| Databáze: | OpenAIRE |
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