Power supply ripple reduction techniques for switched-capacitor circuits
| Autor: | Sang-Yun Baek, B.W. Lee, Y.S. Bae |
|---|---|
| Rok vydání: | 2002 |
| Předmět: |
Very-large-scale integration
Digital electronics Engineering Analogue electronics business.industry Transistor Ripple Electrical engineering Hardware_PERFORMANCEANDRELIABILITY Switched capacitor law.invention Electric power transmission law Integrator Hardware_INTEGRATEDCIRCUITS Electronic engineering business Hardware_LOGICDESIGN |
| Zdroj: | 1991., IEEE International Sympoisum on Circuits and Systems. |
| DOI: | 10.1109/iscas.1991.176680 |
| Popis: | In mixed-mode MOS VLSI circuits switching noises generated in digital circuits are inevitably coupled into analog circuits through commonly shared power lines and substrate layer. Three design techniques to reduce the power ripple coupling, which include optimizing individual SC integrators, minimizing input transistor area and applying a stable bias potential, are described. Experimental results using the optimizing technique show more than 8-dB ripple reduction in a switched-capacitor circuit. > |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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