High-Level Synthesis of Key-Obfuscated RTL IP with Design Lockout and Camouflaging
| Autor: | Love Kumar Sah, Srinivas Katkoori, Sheikh Ariful Islam |
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| Rok vydání: | 2020 |
| Předmět: |
Scheme (programming language)
Computer science business.industry 020206 networking & telecommunications 02 engineering and technology Computer Graphics and Computer-Aided Design 020202 computer hardware & architecture Computer Science Applications Application-specific integrated circuit High-level synthesis Embedded system Obfuscation 0202 electrical engineering electronic engineering information engineering Hardware obfuscation Key (cryptography) Graph (abstract data type) Electrical and Electronic Engineering Field-programmable gate array business Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION computer Hardware_LOGICDESIGN computer.programming_language |
| Zdroj: | ACM Transactions on Design Automation of Electronic Systems. 26:1-35 |
| ISSN: | 1557-7309 1084-4309 |
| Popis: | We propose three orthogonal techniques to secure Register-Transfer-Level (RTL) Intellectual Property (IP). In the first technique, the key-based RTL obfuscation scheme is proposed at an early design phase during High-Level Synthesis (HLS). Given a control-dataflow graph, we identify operations on non-critical paths and leverage synthesis information during and after HLS to insert obfuscation logic. In the second approach, we propose a robust design lockout mechanism for a key-obfuscated RTL IP when an incorrect key is applied more than the allowed number of attempts. We embed comparators on obfuscation logic output to check if the applied key is correct or not and a finite-state machine checker to enforce design lockout. Once locked out, only an authorized user (designer) can unlock the locked IP. In the third technique, we design four variants of the obfuscating module to camouflage the RTL design. We analyze the security properties of obfuscation, design lockout, and camouflaging. We demonstrate the feasibility on four datapath-intensive IPs and one crypto core for 32-, 64-, and 128-bit key lengths under three design corners (best, typical, and worst) with reasonable area, power, and delay overheads on both ASIC and FPGA platforms. |
| Databáze: | OpenAIRE |
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