Design of High Performance HMRPD Network on Chip Interconnect for Neuromorphic Architectures
| Autor: | Gopalakrishnan Seetharaman, Jayshree, Debadatta Pati |
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| Rok vydání: | 2021 |
| Předmět: |
Interconnection
Computer science 05 social sciences 050301 education Throughput Topology (electrical circuits) Network topology Computer Science::Hardware Architecture Network on a chip Neuromorphic engineering Computer architecture Scalability Bandwidth (computing) 0501 psychology and cognitive sciences 0503 education 050104 developmental & child psychology |
| Zdroj: | 2020 3rd International Conference on Energy, Power and Environment: Towards Clean Energy Technologies. |
| Popis: | An emerging neural network consists of larger core chips that rely on the network-on-chip (NoC) based interconnection to control the massive volume of inter-neuron traffic. The NoC interconnect renders high flexibility as it solves one of the critical challenges of reconfigurable neural-networks in hardware implementation. In this paper, a novel two-dimensional (2-D) hybrid of mesh-ring with partial diagonal link (HMRPD) topology has been proposed for neuromorphic architectures. The proposed architecture has been examined in terms of average distance, hope count, and core count of application from source to destination. The analysis shows that the proposed HMRPD topology has low communication costs, high scalable due to small diameter, average distance, and high bandwidth. Finally, a comparison has been performed with the existing topology for neural-network hardware accelerators. Moreover, the proposed HMRPD topology reduces latency and improves the throughput of neural information processing. |
| Databáze: | OpenAIRE |
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