| Autor: |
Koichiro Ishibashi, K. Norisue, T. Nakazawa, Kunio Uchiyama, Ikuya Kawasaki, Suguru Tachibana, I. Kudoh, Shigezumi Matsui, R. Izawa, Junichi Nishimoto, Yasuhisa Shimazaki, Susumu Narita, K. Hirose, M. Yamamoto, Shinichi Yoshioka |
| Rok vydání: |
2002 |
| Předmět: |
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| Zdroj: |
Digest of Technical Papers., Symposium on VLSI Circuits.. |
| Popis: |
A low-power single-chip RISC microprocessor has been designed. It based on Hitachi's SH architecture with multiple page-size MMU. An automatic-power-save cache memory reduces the power dissipation at low frequencies, Two low-power modes and a module-stop function are software programmable for system power management. MMU supports 4 KB and 1 KB page-sizes by 4-way set-associative TLB. The chip using 0.5 um CMOS technology is fabricated, and achieves 60 Dhrystone MIPS and keeps 600 mW (max.), 60 MHz at worst condition. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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