A Self-Tuning IoT Processor Using Leakage-Ratio Measurement for Energy-Optimal Operation
| Autor: | Mehdi Saligane, Yiqun Zhang, Yejoong Kim, Satoru Miyoshi, David Blaauw, Masaru Kawaminami, Jeongsup Lee, Dennis Sylvester, Seokhyeon Jeong, Jongyup Lim, Wootaek Lim, Qing Dong, Makoto Yasuda |
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| Rok vydání: | 2020 |
| Předmět: |
Battery (electricity)
Operating point Computer science business.industry 020208 electrical & electronic engineering Clock rate Electrical engineering Operating frequency Biasing Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology Energy consumption Process corners Dynamic voltage scaling Semiconductor CMOS Dynamic demand Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Voltage regulation Electrical and Electronic Engineering business Voltage Leakage (electronics) |
| Zdroj: | IEEE Journal of Solid-State Circuits. 55:87-97 |
| ISSN: | 1558-173X 0018-9200 |
| DOI: | 10.1109/jssc.2019.2939890 |
| Popis: | Energy-optimal operation is one of the key requirements of the Internet-of-Things (IoT) applications to increase battery life. In this article, using a combination of dynamic voltage scaling (DVS) and adaptive body biasing (ABB), the energy-optimal operation is achieved with a given fixed operating frequency determined by application demands. Based on the observation that the ratio of leakage power to dynamic power can be an accurate indicator for the optimal operating point, the proposed method dynamically tracks the minimum energy operating points by adjusting supply voltage and body bias with very low hardware and power overhead. A custom dc–dc converter for supply voltage regulation and charge pumps for body bias generation were implemented with the proposed method in a Cortex-M0 processor. Since SRAM is included in the same energy optimization loop as the processor, a custom SRAM was designed to match the processor speed. The design is fabricated in an Mie Fujitsu Semiconductor (MIFS) 55-nm deeply depleted channel (DDC) CMOS and the proposed approach achieves energy consumption within 4.6% of optimal at 1 MHz across five process corners and temperatures from −20 °C to 125 °C. The fabricated processor achieves 6.4 pJ/cycle at 0.55-V and 500-kHz clock frequency. |
| Databáze: | OpenAIRE |
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