Design for High Reliability of CMOS IC With Tolerance on Total Ionizing Dose Effect
| Autor: | Minwoong Lee, Nam-Ho Lee, Seong-Ik Cho, Jong-Yeol Kim |
|---|---|
| Rok vydání: | 2020 |
| Předmět: |
010302 applied physics
Materials science business.industry Transistor Hardware_PERFORMANCEANDRELIABILITY Integrated circuit design Integrated circuit 01 natural sciences Electronic Optical and Magnetic Materials law.invention CMOS Application-specific integrated circuit law 0103 physical sciences MOSFET Hardware_INTEGRATEDCIRCUITS Optoelectronics Parasitic extraction Hardware_ARITHMETICANDLOGICSTRUCTURES Electrical and Electronic Engineering Safety Risk Reliability and Quality business Radiation hardening Hardware_LOGICDESIGN |
| Zdroj: | IEEE Transactions on Device and Materials Reliability. 20:459-467 |
| ISSN: | 1558-2574 1530-4388 |
| DOI: | 10.1109/tdmr.2020.2994390 |
| Popis: | As the standard complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) generates a leakage current due to ionizing radiation reacting with silicon in a radiological environment, radiation hardening of CMOS devices is being actively investigated. If a radiation-tolerant IC (RTIC) is designed, it is very important to examine the design possibility of an application specific IC (ASIC) that uses a radiation-tolerant MOS field-effect transistor (MOSFET). This study developed a new RTIC design using an I-gate structure that is more effective in terms of time, cost, and reliability than the existing RTMOSFET. Because an RTIC with an I-gate structure can be fabricated via the usual full-custom IC design process, it can be produced after its reliability is ensured based on post-layout simulation results, which are obtained by layout parasitic extraction (LPE). To realize the possibility of such fabrication, radiation-tolerant digital and analog ICs were designed and fabricated in the standard 0.18- $\mu \text{m}$ CMOS process, and an irradiation test was conducted up to a total dose of approximately 2 Mrad. Accordingly, the radiation damage in the standard IC and the radiation tolerance of the RTIC were identified. Consequently, we have proposed and verified an efficient radiation-tolerant ASIC design solution. |
| Databáze: | OpenAIRE |
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