A 72 dB-DR 465 MHz-BW Continuous-Time 1-2 MASH ADC in 28 nm CMOS
| Autor: | Wenhua William Yang, Hajime Shibata, Jose Barreiro Silva, Trevor Clifford Caldwell, Yunzhi Dong, Richard Schreier, Jialin Zhao, Qingdong Meng, Jeffrey Gealow, Zhao Li, Donald Paterson |
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| Rok vydání: | 2016 |
| Předmět: |
Physics
business.industry Quantization (signal processing) 020208 electrical & electronic engineering Electrical engineering Lattice phase equaliser 02 engineering and technology computer.file_format Flash ADC Chip 020202 computer hardware & architecture CMOS Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering Hardware_ARITHMETICANDLOGICSTRUCTURES Electrical and Electronic Engineering Cmos process business computer dBFS |
| Zdroj: | IEEE Journal of Solid-State Circuits. 51:2917-2927 |
| ISSN: | 1558-173X 0018-9200 |
| Popis: | This paper presents a continuous-time (CT) multi-stage noise-shaping (MASH) ADC in 28 nm CMOS. The MASH ADC uses a first-order front-end stage to digitize the input signal and a second-order back-end stage to digitize the quantization noise of the coarse flash ADC inside the front-end. An RC lattice filter and a current-steering DAC are utilized to extract the front-end coarse quantization residue. The prototype MASH ADC chip built in a 28 nm CMOS process is clocked at 8 GHz with an OSR of 8.6, providing a signal bandwidth of 465 MHz. The ADC achieves a DR of 72 dB and an average small-signal NSD of −160 dBFS/Hz. The peak SNR is 68 dB and the peak SNDR is 67 dB. The IM3 is −88 dBFS with two −9 dBFS tones at the band edge. The ADC consumes 890 mW of power from +1.8/1.0/-1.0 V supplies and achieves a thermal noise FOM of 159 dB. |
| Databáze: | OpenAIRE |
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