| Popis: |
This paper presents a 2-stage CMOS power amplifier for the 1.75 GHz band using a 0.18-μm CMOS process. Using ADS simulation, a power gain of 28 dB and an efficiency of 45 % at an 1dB compression point of 27 dBm were achieved. The implemented CMOS power amplifier delivered an output power of up to 24.8 dBm with a power-added efficiency of 41.3 % and a power gain of 22.9 dB. For a 16-QAM uplink LTE signal, the PA exhibited a power gain of 22.6 dB and an average output power of 23.1 dBm with a PAE of 35.1 % while meeting an ACLR(Adjacent Channel Leakage Ratio) level of 30 dBc. Key words: Power Amplifier, CMOS, LTE K 9,LM N /2014OP QRST UVSWXYZ[\] M ^(NRF-2014H1A2A1019955)._ `a bc d%b Revised August 11, 2014 ; Accepted September 5, 2014. (ID No. 20140701-06S)Corresponding Author: Youngoo Yang (e-mail: yang09@.skku.edu) f. 서 론 gh %&/ij,kl Bm %& /\nH Ho". %& /\n Hpq rst,eu ,avw\nH Hrx". XyzX e{/ %& |+}~ Irx". -, *|+}~BGaAs , r45w9$ XIHj 9 x". XICMOS U, GaAsG Gc*Hj r, CHU9 x". ghCMOS /k w9N BmCMOS , , H" Xrx" |
