Design of Wide - range Clock and Data Recovery Circuit based Dual-loop DLL using 2-step DPC

Autor:	Ki-Sang Jung, Kang-Jik Kim, Seong-Ik Cho, Guihan Ko
Rok vydání:	2012
Předmět:	Computer science Serial communication business.industry Data recovery circuit Clock rate Dual loop Data recovery Delay-locked loop Electronic engineering Range (statistics) Electrical and Electronic Engineering business Computer hardware Jitter
Zdroj:	The Transactions of The Korean Institute of Electrical Engineers. 61:324-328
ISSN:	1975-8359
Popis:	A recovered jitter of CDR(Clock and Data Recovery) Circuit based on Dual-loop DLL(Delay Locked Loop) for data recovery in high speed serial data communication is changed by depending on the input data and reference clock frequency. In this paper, 2-step DPC which has constant jitter performance for wide-range input frequency is proposed. The designed prototype 2-step CDR using proposed 2-step DPC has operation frequency between 200Mbps and 4Gbps. Average delay step of 2-step DPC is 10ps. Designed CDR circuit was tested with 0.18um CMOS process.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::cc191d1f1803745f09b42da783af744e https://doi.org/10.5370/kiee.2012.61.2.324 Zobrazit plný text záznamu