K-nearest neighbor algorithm implementation on FPGA using high level synthesis
| Autor: | Zhehao Li, Zhi-Hua Feng, Xuegong Zhou, Jifang Jin |
|---|---|
| Rok vydání: | 2016 |
| Předmět: |
Computer science
Interface (computing) Hardware description language 02 engineering and technology Parallel computing 030204 cardiovascular system & hematology 020202 computer hardware & architecture 03 medical and health sciences Statistical classification 0302 clinical medicine High-level synthesis Pattern recognition (psychology) 0202 electrical engineering electronic engineering information engineering Hardware acceleration Field-programmable gate array Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION Algorithm computer Abstraction (linguistics) computer.programming_language |
| Zdroj: | 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT). |
| DOI: | 10.1109/icsict.2016.7998989 |
| Popis: | The K-Nearest Neighbor (K-NN) algorithm is one of the most common classification algorithms and widely used in pattern recognition and data mining. K-NN hardware acceleration is necessary for applications with massive high-dimensional data. High level synthesis (HLS) is an increasingly adopted technique in digital circuit design, which can help to raise the abstraction levels. In this paper, we exploit the parallelism and pipelining opportunities and apply the memory-mapped AXI4-Master Interface to implement K-NN on an FPGA using HLS. The evaluation result shows that our HLS-based solution is 35.1× faster than a general purpose processor (GPP) based implementation, and comparable to hardware description language (HDL) based implementations, while our HLS-based solution largely reduces the development complexity and cost. |
| Databáze: | OpenAIRE |
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