| Autor: |
Ali Sheikholeslami, M. Sadegh Jalali, Clifford Ting, Hirotaka Tamura, Behrooz Abiri, Masaya Kibune |
| Rok vydání: |
2013 |
| Předmět: |
|
| Zdroj: |
2013 IEEE Asian Solid-State Circuits Conference (A-SSCC). |
| DOI: |
10.1109/asscc.2013.6691054 |
| Popis: |
This paper uses a 3-bit ADC to blindly sample the received data at 3× the baud rate to recover the data. By moving from 2× to 3× sampling, we reduce the required ADC resolution from 5-bit to 3-bit, thereby reducing the overall power consumption by a factor of 2. Measurements from our fabricated test chip in Fujitsu's 65nm CMOS show a high frequency jitter tolerance of 0.19UIpp for a 5Gbps PRBS31 with a 16" FR4 channel. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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