A 2.41-pJ/bit 5.4-Gb/s Dual-Loop Reference-Less CDR With Fully Digital Quarter-Rate Linear Phase Detector for Embedded DisplayPort
| Autor: | Young-Soo Ryu, Jin-Ku Kang, Jae-Wook Yoo, Yong-Hwan Moon, Kyung-Sub Son, Sang Ho Kim |
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| Rok vydání: | 2019 |
| Předmět: |
Physics
Bandgap voltage reference DisplayPort 020208 electrical & electronic engineering Detector 02 engineering and technology Phase detector law.invention Phase-locked loop Hardware and Architecture law 0202 electrical engineering electronic engineering information engineering Electronic engineering Electrical and Electronic Engineering Phase frequency detector Linear phase Jitter |
| Zdroj: | IEEE Transactions on Circuits and Systems I: Regular Papers. 66:2907-2920 |
| ISSN: | 1558-0806 1549-8328 |
| Popis: | This paper describes a low-power reference-less 5.4-Gb/s clock and data recovery (CDR) circuit with a fully digital quarter-rate linear phase detector (QLPD) having an extended pulse width output. By using a fully digital circuit and merging XOR function with charge pump, the power efficiency and linearity of the phase detector are improved. The proposed QLPD responds correctly up to 0.75 UI of phase difference at 5.4 Gb/s. The CDR was designed to conform to Embedded DisplayPort (eDP) standard of the Video Electronics Standards Association (VESA). The proposed CDR circuit has been fabricated using a 40-nm CMOS technology. The jitter tolerance (JTOL) margin was measured at 0.75 UI, which is 20% higher than the eDP specification of 0.624 UI at the 20-MHz jitter frequency. BER was measured as less than 10−12 with a 27−1 pseudo random bit sequence (PRBS) pattern. The CDR consumes 12.99 mW, including a bandgap reference circuit and power efficiency achieving 2.41 pJ/bit at 5.4 Gb/s. The area of the proposed CDR is 0.13 mm2. |
| Databáze: | OpenAIRE |
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