Time Discrete Voltage Sensing and Iterative Programming Control for a 4F2 Multilevel CBRAM

Autor:	Corvin Liaw, Peter Schrögmeier, G. Muller, S. Bournat, Stefan Dietrich, Ralf Symanczyk, Michael Markert, Heinz Hönigschmid, Michael Angerbauer, L. Altimime, Milena Ivanov
Rok vydání:	2007
Předmět:	Read-only memory Bridging (networking) Computer science Programmable metallization cell Memory architecture Voltage sensing Electronic engineering Content-addressable storage Integrated circuit design Electronic circuit
Zdroj:	2007 IEEE Symposium on VLSI Circuits.
DOI:	10.1109/vlsic.2007.4342708
Popis:	Multilevel read/write circuits developed for a 90 nm, 4F2, 1T1CBJ (1-transistor/1-conductive bridging junction) 4Mb CBRAM core are described for the first time. The design uses an on-pitch time-discrete voltage sensing scheme and employs a bitline (BL) charge balancing reference as well as a self-timed iterative program concept. Random read cycle times ap0.7 mus and random write cycle times ap1.35 mus are achieved.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::cbc843f0aaec88c42212b4d7058daf0f https://doi.org/10.1109/vlsic.2007.4342708 Zobrazit plný text záznamu