Function-Safe Vehicular AI Processor with Nano Core-In-Memory Architecture
| Autor: | Kyoung-Seon Shin, Jeongmin Yang, Chun-Gi Lyuh, Jaehoon Chung, Jinho Han, Young-Su Kwon, Minseok Choi, Yong Cheol Peter Cho, Hyun-Mi Kim, Chan Kim |
|---|---|
| Rok vydání: | 2019 |
| Předmět: |
0209 industrial biotechnology
Multi-core processor Artificial neural network Computer science business.industry 02 engineering and technology FLOPS Microarchitecture 020901 industrial engineering & automation Embedded system Datapath Memory architecture 0202 electrical engineering electronic engineering information engineering 020201 artificial intelligence & image processing Electronics business |
| Zdroj: | AICAS |
| DOI: | 10.1109/aicas.2019.8771603 |
| Popis: | State-of-the-art neural network accelerators consist of arithmetic engines organized in a mesh structure datapath surrounded by memory blocks that provide neural data to the datapath. While server-based accelerators coupled with server-class processors are accommodated with large silicon area and consume large amounts of power, electronic control units in autonomous driving vehicles require power-optimized, ‘AI processors’ with a small footprint. An AI processor for mobile applications that integrates general-purpose processor cores with mesh-structured neural network accelerators and high speed memory while achieving high-performance with low-power and compact area constraints necessitates designing a novel AI processor architecture. We present the design of an AI processor for electronic systems in autonomous driving vehicles targeting not only CNN-based object recognition but also MLP-based in-vehicle voice recognition. The AI processor integrates Super-Thread-Cores (STC) for neural network acceleration with function-safe general purpose cores that satisfy vehicular electronics safety requirements. The STC is composed of 16384 programmable nano-cores organized in a mesh-grid structured datapath network. Designed based on thorough analysis of neural network computations, the nano-core-in-memory architecture enhances computation intensity of STC with efficient feeding of multi-dimensional activation and kernel data into the nano-cores. The quad function-safe general purpose cores ensure functional safety of Super-Thread-Core to comply with road vehicle safety standard ISO 26262. The AI processor exhibits 32 Tera FLOPS, enabling hyper real-time execution of CNN, RNN, and FCN. |
| Databáze: | OpenAIRE |
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