A 12-Bit 31.1-$\mu$ W 1-MS/s SAR ADC With On-Chip Input-Signal-Independent Calibration Achieving 100.4-dB SFDR Using 256-fF Sampling Capacitance
| Autor: | Baozhen Chen, Junhua Shen, Anping Liu, Frederick Chalifoux, Akira Shikata |
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| Rok vydání: | 2019 |
| Předmět: |
Spurious-free dynamic range
12-bit Calibration (statistics) Computer science 020208 electrical & electronic engineering Transistor Linearity Successive approximation ADC 02 engineering and technology Capacitance law.invention Capacitor Sampling (signal processing) law Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering Electrical and Electronic Engineering |
| Zdroj: | IEEE Journal of Solid-State Circuits. 54:937-947 |
| ISSN: | 1558-173X 0018-9200 |
| DOI: | 10.1109/jssc.2018.2883084 |
| Popis: | A 12-bit 31.1- $\mu \text{W}$ 1-MS/s successive approximation register analog-to-digital converter (ADC) with on-chip input-signal-independent calibration achieving 100.4-dB spurious-free dynamic range is presented. The proposed calibration overcomes the drawbacks of the conventional split-ADC calibration while maintaining fast convergence. The calibration only needs one ADC and is input signal independent. Three techniques are proposed to help achieve this, including shuffling of mismatched MSB capacitors, MSB–LSB swapping, and partial MSB unit-capacitor dithering. In addition, partial bit trial and split-bottom switching circuit techniques are proposed. Silicon results fully validated the design and show 16-bit linearity with only 256-fF sampling capacitance. |
| Databáze: | OpenAIRE |
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