| Autor: |
T.F. McNelly, M. Blackwell, Jung-Hui Lin, Matthew A. Thompson, F. Nkansah, C. Philbin, Asanga H. Perera, James R. Pfiester, W. Fell, T. Lii, James D. Hayden, Y.-C. Ku, C.K. Subramanian, C.J. Sun, S. Ajuria, Michael P. Woo, B.M. James |
| Rok vydání: |
2002 |
| Předmět: |
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| Zdroj: |
Proceedings of International Electron Devices Meeting. |
| DOI: |
10.1109/iedm.1995.499368 |
| Popis: |
A high performance 0.25 /spl mu/m CMOS process has been developed for fast static RAMs, featuring retrograde wells, shallow trench isolation with 0.55 /spl mu/m active pitch, a 55 /spl Aring/ nitrided gate oxide, 0.25 /spl mu/m polycide gate surface channel NMOS and PMOS transistors with drive currents of 630 and 300 /spl mu/A//spl mu/m respectively at an off-leakage of 10 pA//spl mu/m, overgated TFTs with an on/off ratio greater than 6/spl middot/10/sup 5/, stacked capacitors for improved SER, five levels of polysilicon planarized by chemical-mechanical polishing (CMP), with two self-aligned interpoly contacts and a tungsten interpoly plug (WIP) that connects 3 poly layers without parasitic diodes, 0.35 /spl mu/m contacts and a 0.625 /spl mu/m metal pitch. A split word-line bitcell was scaled to an area of 3.74 /spl mu/m/sup 2/ using 0.25 /spl mu/m design rules. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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