A low-PDP and low-area repeater using passive CTLE for on-chip interconnects

Autor:	Chih-Kong Ken Yang, Mau-Chung Frank Chang, Ming-Shuan Chen
Rok vydání:	2015
Předmět:	Repeater Engineering CMOS business.industry Bandwidth (signal processing) Electrical engineering Electronic engineering Inverter System on a chip business
Zdroj:	VLSIC
DOI:	10.1109/vlsic.2015.7231273
Popis:	This paper presents an improved repeater circuit that preserves the advantages of the inverter repeater and achieves a lower power, delay, and area by applying proper equalization. Designed and measured in 65nm CMOS technology, the proposed repeater achieves 44% lower power-delay product (PDP) while occupies 46% lower area.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::cabe3ab02d69c8f9f3f897b8f3a0adc0 https://doi.org/10.1109/vlsic.2015.7231273 Zobrazit plný text záznamu