A Power-Efficient Mixed-Signal Smart ADC Design With Adaptive Resolution and Variable Sampling Rate for Low-Power Applications
| Autor: | Ho-Yin Lee, Jocelyn Flores Villaverde, Chih-Hao Tseng, Kuei-An Lo, Shih-Lun Chen, Danny Wen-Yaw Chung, Ting-Lan Lin |
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| Rok vydání: | 2017 |
| Předmět: |
Lossless compression
Engineering business.industry 020208 electrical & electronic engineering 010401 analytical chemistry Mixed-signal integrated circuit Data_CODINGANDINFORMATIONTHEORY 02 engineering and technology Chip 01 natural sciences 0104 chemical sciences Transmission (telecommunications) Application-specific integrated circuit 0202 electrical engineering electronic engineering information engineering Electronic engineering Entropy encoding Electrical and Electronic Engineering business Instrumentation Encoder Data compression |
| Zdroj: | IEEE Sensors Journal. 17:3461-3469 |
| ISSN: | 2379-9153 1530-437X |
| DOI: | 10.1109/jsen.2017.2680472 |
| Popis: | With the rapid development of portable electronics, wearable devices have become widely used to monitor body signals for long-term health care and home care applications. They detect vital signals through physiological sensors and then transmit them to a cloud database for evaluation and monitoring purposes through wireless communication systems. In this paper, a smart analog-to-digital converter (ADC) was realized by a mixed-signal application-specific integrated circuit (ASIC) based on adaptive resolution and lossless compression techniques for electrocardiogram (ECG) signal monitoring. The sampling clock for the ADC can be adaptively selected according to the characteristic of the signals. The lossless encoder consists of trend forecasting and entropy coding modules. The transmission data rate was decreased efficiently by adaptive resolution and lossless compression techniques. The chip aims to meet the low power consumption for the design, because it reduced the signal transmission rate and maintained high-quality ECG signal detection. The proposed mixed-signal ASIC design was realized using a 0.18- $\mu \text{m}$ CMOS process with a total power consumption of $78.8~\mu \text{W}$ when operating at 1 kHz and a total chip area of 850 $\times 850~\mu \text{m}^{2}$ . |
| Databáze: | OpenAIRE |
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