| Autor: |
Alpha Agape Gopalai, Adib Kabir Chowdhury, Bakri Madon, Ashutosh Kumar Singh, Lenin Gopal |
| Rok vydání: |
2014 |
| Předmět: |
|
| Zdroj: |
2014 IEEE International Conference on Control System, Computing and Engineering (ICCSCE 2014). |
| DOI: |
10.1109/iccsce.2014.7111144 |
| Popis: |
Reversible computation plays an important role in low power circuit design and efficient energy recycling. In this paper, a switch controlled efficient Reversible Full Adder/Subtractor (RFAS) is presented. RFAS block is further used in the construction of n-bit adder/subtractor. The proposed design is analyzed and compared against the existing reversible techniques. Features such as, hardware cost, logic calculation and gate count etc. are investigated to show the efficiency of the design. Simulation results are verified using Altera Quartus II and ModelSim software. Observations suggest that the circuit offers lesser hardware complexity compared to the existing reversible full adder. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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