23.6 A 0.6V 4.266Gb/s/pin LPDDR4X interface with auto-DQS cleaning and write-VWM training for memory controller
| Autor: | Kyoung-Hoi Koo, Sang-Soo Park, Eun-Su Kim, Sanghune Park, Dae-Ro Kim, Soo-Min Lee, Suho Kim, Sungho Park, Sanghyun Lee, Lee Hyung-Kweon, Jinho Choi, Seokkyun Ko, Kwanyeob Chae, Yoonjee Nam, Sukhyun Jung, Jihun Oh, Jongryun Choi |
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| Rok vydání: | 2017 |
| Předmět: |
Engineering
Data strobe encoding business.industry 020208 electrical & electronic engineering Electrical engineering 020206 networking & telecommunications 02 engineering and technology Memory controller Duty cycle Logic gate Delay-locked loop 0202 electrical engineering electronic engineering information engineering Electronic engineering business NMOS logic Voltage reference Dram |
| Zdroj: | ISSCC |
| DOI: | 10.1109/isscc.2017.7870429 |
| Popis: | Although the LPDDR4 interface has enabled industry requirements, such as low power consumption and high bandwidth, additional evolution of the current LPDDR4 performance is expected. To respond to the need for more power efficient devices with higher bandwidth, a 2nd generation LPDDR4 (referred to as LPDDR4X), with extreme low power and extended performance, has been developed in this work. In the controller, the output drivers for data signal (DQ) and data strobe signal (DQS) dominate the power consumption. An efficient method to reduce the output driver power is to reduce the supply voltage (V DDQ ) [1]. A low voltage-swing terminated logic (LVSTL) [2] can support this solution by changing the operation region of the pull-up NMOS transistor from the saturation region to the triode region. However, another power supply whose minimum value is V TH_NMOS +V DDQ is required for the pull-up NMOS transistor to serve as source-series termination. In this work, P-over-N topology replaces LVSTL and allows for the use of a single V DDQ (0.6V), thus reducing pre-driver power. Another major improvement in the proposed LPDDR4X controller is that it has functions to compensate for the large variation of DQS output transition time from CK (Δt DQSCK ) [3] due to the lack of a delay locked loop (DLL) in LPDDR4 DRAM [4]. Furthermore, the reference voltage on DRAM and the duty cycle of both DQ and DQS are initially calibrated to increase the valid window margin (VWM) during write operations. VWM is the time interval where all DQs remain valid before and after DQS edge in order to capture DQs correctly. |
| Databáze: | OpenAIRE |
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