A 2.4 GHz Fractional-N Frequency Synthesizer With High-OSR ΔΣ Modulator and Nested PLL

Autor:	SeongHwan Cho, Dongmin Park, Pyoungwon Park
Rok vydání:	2012
Předmět:	Frequency synthesizer Engineering business.industry Ring oscillator Delta-sigma modulation Noise (electronics) Phase-locked loop Frequency divider Direct digital synthesizer Phase noise Hardware_INTEGRATEDCIRCUITS Electronic engineering Electrical and Electronic Engineering business
Zdroj:	IEEE Journal of Solid-State Circuits. 47:2433-2443
ISSN:	1558-173X 0018-9200
Popis:	This paper presents a nested-PLL architecture for a low-noise wide-bandwidth fractional-N frequency synthesizer. In order to reduce the quantization noise, operating frequency of ΔΣ modulator (DSM) is increased by using an intermediate output of feedback divider. A PLL which serves as an anti-alias filter is added to suppress noise aliasing caused by the divider. Prototype implemented in a 0.13 μm CMOS using ring VCOs achieves 26.3 dB of quantization noise suppression while consuming 15.2 mW and occupying 0.17 mm2.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::ca26756bb11e8918690b03ddce3cfd7c https://doi.org/10.1109/jssc.2012.2209809 Zobrazit plný text záznamu