| Popis: |
Since the advent of non-planar metal-oxide-semiconductor (MOS) transistors, embodied by the three-dimensional fin field-effect transistors (finFETs), there has been a rising need for fast in-line metrology solutions for the electrical characterization of nanometer-wide trenches filled with semiconducting materials. Indeed, on such narrow structures, conventional four point probe fails, mostly due to the challenging alignment of the four millimeter-sized and -spaced probes to the nanoscale trenches. Subsequently, at the expense of extra processing cost and time, the electrical characterization of these state-of-the-art devices is now performed at metal-1 on fins connected by metal contacts in Kelvin resistor or transmission line structures [1]. However, a very promising technique to solve the need for electrical resistance measurements of narrow fins without the need for metal contacts is the micro four-point probe. This four-point probe technique where the probes and probe distance have been downscaled to a few micrometer size has been successfully applied to a myriad of blanket materials, ranging from multilayered metal stacks [2] to semiconductors [3], two-dimensional materials [4] and even single nanowires [5]. Advantageously, micro-probes have allowed a smaller sampling volume and a minimized sensitivity to junction leakage in blanket samples [6] but they are also much easier to align to nanoscale trenches. In this contribution, we evaluate the capabilities of micro four-point probe, as implemented in the fully automatic microHALL®-A300 tool of CAPRES A/S, for the in-line resistance measurement of single oxide-isolated nanoscale fin-like structures. We start by showing that this tool is capable of contacting the four probes with single fins with widths down to 20 nm, i.e. three orders of magnitude smaller than the total 24 μm distance between the two outermost pins. Next, we investigate the measured resistance values to evaluate whether the measured resistance values can be correctly attributed to the semiconducting material located inside the trench. Many parasitic conduction paths could indeed still lead to the underestimation of the actual resistance of these narrow features. In this paper, we evaluate how to minimize the possible contribution of the two most probable parasitic resistances. First of all, we consider the contribution of multiple fins which could be contacted in parallel when the distance between two consecutive fins is shorter than the size of the probe contacts. To minimize this first contribution, we use atomic force microscopy (AFM) to measure the lateral extent of the probe imprints and only focus on arrays where the fin distance is larger than the imprint. Second and most important of all, for very high fin resistances (e.g. narrow fins made of lowly doped material), current may significantly leak into the substrate [2,6]. This second contribution is investigated in two different manners. Since the impact of such parasitic resistances rises as the feature width decreases, we study the resistance-to-width correlation in fins with widths ranging from 20 nm to 10 μm. Also we investigate the resistances measured in the different available configurations (A, B and C) as their ratio offers valuable information on the dimensionality of the current path (one-dimensional in the trench and two-dimensional in the substrate) [4]. Our study concludes on recommendations targeting the accurate resistance measurement of sub-50-nm fins. [1] D. K. Schroder, Semiconductor material and device characterization, 3rd ed., Chap I, Wiley-Interscience (2006) [2] D.C. Worledge et al., Appl. Phys. Lett. 83, 84 (2003) ; D. Kjaer, et al., Meas. Sci. Technol. 26, 045602 (2015). [3] D. H. Petersen et al., J. Vac. Sci. Technol. B 28, C1C27 (2010); T. Clarysse, et al., Mater. Sci. and Eng. B 154, 24 (2008); T. Clarysse et al., J. Vac. Sci. Technol. B 28, C1C8 (2010) [4] J.D. Buron, et al., Nano Lett. 12, 5074 (2012); J.D. Buron, et al., Nano Lett. 14, 6348 (2014). [5] R. Lin, et al., Nanotechnology 15, 1363 (2004) ; [6] R. Lin et al., AIP Conf. Proceedings 1496, 175-178 (2012); C.L. Petersen, et al., RTP 2006 (IEEE NY, 2006), 153-157; T. Clarysse et al., Mater. Res. Soc. Symp. Proc. 912, 197 (2006). |
